Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including a fuse circuit in which an address corresponding to a repair target memory cell is programmed.
In general, a semiconductor memory device including a double data rate synchronous DRAM (DDR SDRAM) is provided with a large number of memory cells. As fabrication technologies are being advanced, the integration density of the semiconductor memory device gradually increases and the number of memory cells provided in the semiconductor memory device also gradually increases. When a fail occurs in any one of the memory cells, a corresponding semiconductor memory device may not perform a desired operation and thus may be discarded as a defective product. As fabrication technologies for semiconductor memory devices are being advanced, a fail may occasionally occur in memory cells. If an entire semiconductor memory device is discarded as a defective product due to such fails, the product yield may suffer. In order to address such a concern, redundancy memory cells as well as normal memory cells are provided within a semiconductor memory device. When a fail occurs in a normal memory cell, it is replaced with a redundancy memory cell. A failed normal memory cell which is to be replaced with a redundancy memory cell may be referred to as a “repair target memory cell.”
Meanwhile, a semiconductor memory device includes a fuse circuit which can program an address corresponding to a repair target memory cell (hereinafter, referred to as a repair target address). A programming refers to a series of operations for storing a repair target address in a fuse circuit.
In general, a fuse circuit includes a plurality of fuses. Representative methods for programming such fuses include a laser cutting method and an electrical cutting method. According to the laser cutting method, a cutting target fuse corresponding to a repair target address is blown and cut by a laser beam. According to the electrical cutting method, a cutting target fuse is melted and cut by applying an over-current thereto. The laser cutting method may be performed at a wafer level which is prior to a package level of a semiconductor memory device, and the electric cutting method may performed at a package level. Since the laser cutting method is simpler than the electrical cutting method, it is widely used. However, the electrical cutting method is also widely used because it can be performed even after the packaging step.
As described above, the address corresponding to the repair target memory cell is programmed in the fuse circuit. That is, the repair target address is programmed in the fuse provided in the fuse circuit, and the semiconductor memory device performs the repair operation by using the programmed repair target address. In other words, when an external address is for accessing the repair target memory cell, the semiconductor memory device can perform the repair operation to access the redundancy memory cell instead of the repair target memory cell by comparing the external address with the programmed repair target address.
FIG. 1 is a circuit diagram illustrating a conventional address fuse unit of a semiconductor memory device.
Referring to FIG. 1, the address fuse unit includes a fuse driving unit 110 and a fuse information output unit 120. The fuse driving unit 110 is enabled in response to a fuse enable signal FSE, and drives a voltage of a first node N1 in response to a repair target address which is programmed in an address fuse F. That is, the address fuse F is in a cut state or in an uncut state according to the repair target address programmed therein, and the voltage of the first node N1 is driven to a logic low level or a logic high level according to whether the address fuse F is in a cut state or an uncut state. Here, the fuse enable signal FSE is activated after a power-up operation starts when a power supply voltage VDD applied to the semiconductor memory device is higher than a certain voltage level.
The fuse information output unit 120 outputs an output signal OUT by inverting or non-inverting an address signal XA corresponding to an external address in response to a voltage level of the first node N1. That is, the output signal OUT is determined according to the voltage level of the first node N1 and the address signal XA. Here, since the voltage of the first node N1 is driven according to whether the address fuse F is in a cut or an uncut state, the output signal OUT is outputted in response to a comparison value between the repair target address programmed in the address fuse F and the address signal XA corresponding to the external address.
Meanwhile, the semiconductor memory device performs an initialization operation according to whether the address fuse F is in a cut or an uncut state after the power-up operation starts. In other words, the fuse enable signal FSE transitions to a logic low level from a logic high level after a power-up operation starts, and the fuse driving unit 110, responding to the fuse enable signal FSE, performs the initialization operation by driving the voltage of the first node N1 according to whether the address fuse F is in a cut or an uncut state, as shown in FIG. 2.
FIG. 2 is a waveform illustrating the initialization operation of the fuse driving unit 110 shown in FIG. 1.
The initialization operation of the fuse driving unit 110 is classified into two types, i.e., <NO CUT> and <CUT>, according to whether the address fuse F is in a cut or an uncut state.
First, referring to FIGS. 1 and 2, a case where the address fuse F is in an uncut state <NO CUT> is described in detail. A first NMOS transistor NM11 of the fuse driving unit 110 is turned on in response to the fuse enable signal FSE of a logic high level, and the voltage level of the first node N1 becomes a logic low level. At this time, since a second NMOS transistor NM12, which is formed as a latch type and receives a signal derived and fed back from the first node N1, is turned on, the voltage level of the first node N1 maintains a logic low level.
When the fuse enable signal FSE transitions to a logic low level from a logic high level after the power-up operation starts, a first PMOS transistor PM11 is turned on and thus the power supply voltage VDD is supplied to the first node N1. Here, due to a conflict between current flowing through the address fuse F and the first PMOS transistor PM11, and current flowing through the second NMOS transistor NM12, the voltage level of the first node N1 increases. As a result, when the address fuse F is in an uncut state, the voltage level of the first node N1 becomes a logic high level.
Next, referring to FIGS. 1 and 2, a case where the address fuse F is in a cut state <CUT> is described in detail. The first NMOS transistor NM11 of the fuse driving unit 110 is turned on in response to the fuse enable signal FSE of a logic high level, and the voltage level of the first node N1 becomes a logic low level. At this time, since the second NMOS transistor NM12, which is formed as a latch type and receives a signal derived and fed back from the first node N1, is turned on, the voltage level of the first node N1 maintains a logic low level.
When the fuse enable signal FSE transitions to a logic low level from a logic high level after the power-up operation starts, the first PMOS transistor PM11 is turned on. At this time, since the address fuse F is in a cut state, the power supply voltage VDD is not supplied to the first node N1. As a result, when the address fuse F is in a cut state, the voltage level of the first node N1 maintains the logic low level.
Meanwhile, an address fuse unit may not be used according to the number of the repair target memory cells. Accordingly, the address fuse F provided in such an address fuse unit may not be programmed. Since the non-programmed address fuse F generally remains in an uncut state, the address fuse unit including the non-programmed address fuse F has a waveform such as a case where the address fuse F is in the uncut state <NO CUT> shown in FIG. 2.
As described above, when the address fuse F is in the uncut state <NO CUT>, the voltage level of the first node N1 increases to a logic high level from a logic low level in the initialization operation. At this time, a conflict between current flowing through the address fuse F and the first PMOS transistor PM11, and current flowing through the second NMOS transistor NM12 occurs at the first node N1. Due to this current conflict, current from several ten mA to several hundred mA may be consumed. As the integration density of the semiconductor memory device increases and the number of memory cells increases, the number of the address fuse units also increases. Accordingly, the increased number of the address fuse units may not be used, increasing unnecessary current consumption due to the current conflict after the power-up operation starts more and more.